This invention relates to semiconductor memories, and more particularly to charge coupled device memories (CCD) comprised of improved memory "cells" or "stages".
During the past several years, much time, effort, and money has gone into the development of high density, low cost memories. This is because the computer industry has continually demanded more and more storage capacity. As a result of this past memory development work, the number of stages per chip has increased from 16 to 64,000. In addition, the cost per stage has been decreased by a factor of approximately 200.
A popular architecture for the CCD memory is the serial-parallel-serial (SPS) organization. Information in the form of charge packets is serially loaded into a shift register. When the register is full, the charge packets are loaded in parallel into a first in-first out stack. The charge packets are then moved in parallel through column transfer channels within the stack. At the stack output, they are loaded in parallel into another shift register. The charge packets are then shifted serially into a detection device.
A major reason for the increase in the number of stages per chip has been the development of small, reliable memory cells. Thousands of these cells are formed on a single chip; and the chips are interconnected to form larger memories. By forming large numbers of memory cells in a chip, large economies in the cost per bit can result if reasonable yields are obtained. However, as the size of a chip increases, the yield decreases; so that the advantage of obtaining a large number of stages per chip by use of a larger chip size is outweighted by reduction in yields. Presently, chips of about 150-250 mils on a side are commonly made in the semiconductor industry. Accordingly, it is desirable to reduce the area occupied by each cell in order to further increase the number of stages per chip.
An important limitation of the prior art cells is that they all have less charge capacity per unit area than is desirable. A high charge capacity per unit area is desired because as the number of stages per chip increases, the size of each cell must necessarily decrease. Thus the amount of charge stored in each cell decreases. Eventually, a point is reached beyond which the cell cannot be reduced further because the amount of charge that the cell can store is indistinguishable from noise. Thus, charge capacity per unit area is a fundamental limitation on the minimum cell size.
Prior art cells are also deficient in a second parameter which is called leakage current. The leakage current is a measure of the quantity of electron-hole pairs that are thermally generated in a cell. These charge carriers are undesirable because they alter the amount of charge that is stored as information, and eventually they totally cancel the information charge. In order to avoid this cancelling effect, the information charge in the cell must be periodically "refreshed" at certain minimum time intervals. The refresh period is inversely proportional to the leakage current in the cell.
Because of these and other limitations in the prior art, and because of the demand for more cells of storage per chip, it is therefore an object of this invention to provide an improved charge coupled device memory.
It is another object of the invention to provide a charge coupled device memory comprised of stages having an increased storage capacity per unit area.
It is still another object of the invention to provide a charge coupled device memory comprised of stages having decreased leakage current while at the same time having increased storage capacity per unit area.